Tips & Tricks

Geometrical drawbeads with Design Table

CATIA V5 offers powerful functionality to modify existing geometry “from outside” via DESIGN TABLE. PAM DIEMAKER for CATIA V5 also supports this procedure with some prerequisites.

How to use Blank Holder functionality in PAM-DIEMAKER for CATIA V5

This video shows how to use Blank Holder functionnality to create mono surface Blank Holder shapes and combination of several Blank Holder patches.

How to create a complex blank holder with PAM-DIEMAKER for CATIA V5

This video shows how the complex blank holder of a double action draw die can be created from multiple segments using a combination of standard CATIA and special PAM-DIEMAKER for CATIA V5 functions all available inside the Blank Holder dialog.

Improve trimming with Overshoot

Trimming in PAM-STAMP can fail due to a too short trimming segment curve leading to not cut properly the blank mesh. This can be solved by using Overshoot option in PAM-DIEMAKER for CATIA V5.

Trim and Shear Angles

Explanations about Trim and Shear Angles

How to define height of constraint UDT profile with respect to the Blankholder?

Method to constrain the height of UDT profile bulge with respect to the Blankholder

How to define tipping for free double parts with existing forming direction?

Recommendation to position properly the free double parts in case the forming direction is predefined.

How to get back the hidden Part Definition after accepting dialogue?

Option to deactivate to get back the hidden part definition after accepting dialogue.

How to improve the update performance on iterations?

Recommendation to optimize the update performance during iterations.

Parallel processing

“To pull a bigger wagon, it is easier to add more horses than to grow a gigantic horse.” This paraphrased quotation nicely expresses the basic concept of parallel processing. The speed of sequential computers has been doubling every eighteen months, according to Moore’s law. However, at any given time, that speed is limited by the state of the art in integrated circuit design and manufacturing. To circumvent that limitation, it is possible to split a given computationally intensive task among multiple processors working simultaneously.